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ibm13q32734bca 32m x 72 registered sdram module 04k8918.c75665b 6/99 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 1 of 15 features ? 200-pin jedec standard, registered 8-byte dual in-line memory module ? 32m x 72 synchronous dram dimm ? performance: ? inputs and outputs are lvttl (3.3v) compatible ? single 3.3v to 3.6v power supply ? single pulsed ras interface ? fully synchronous to positive clock edge ? data mask control ? auto refresh (cbr) and self refresh ? automatic and controlled precharge commands ? programmable operation: -sdram cas latency: 2 -burst type: sequential or interleave -burst length: 2 -operation: burst read and write or multiple burst read with single write ? suspend mode and power down mode ? 12/10/2 addressing (row/column/bank) ? 4096 refresh cycles distributed across 64ms ? parallel presence detect ? card size: 6.05" x 1.50" x 0.320" ? gold contacts ? sdram s in tsoj type ii, 2-high, stacked package description ibm13q32734bca is a registered 200-pin synchro- nous dram dual in-line memory module (dimm) which is organized as a 32mx72 high-speed mem- ory array. the dimm uses eighteen x4 sdrams in 400mil tsoj ii stacked packages. the dimm achieves high speed data transfer rates of up to 66mhz by employing a prefetch/pipeline hybrid architecture that supports the jedec 1n rule while allowing very low burst power. the dimm is intended to comply with all non- optional jedec standards set for the 200-pin regis- tered sdram dimms. all control and address signals are synchronized with the positive edge of an externally supplied clock. they are latched in an on-dimm pipeline register and presented to the sdrams on the fol- lowing clock. prior to any access operation, the cas latency, burst type, burst length, and burst operation type must be programmed into the dimm by address inputs a0-a13 using the mode register set cycle. the dimm uses parallel presence detects imple- mented according to the jedec standard. all ibm 200-pin dimms provide a high performance, flexible 8-byte interface in a 6.05 long high-perfor- mance footprint. related products include both edo dram and sdram unbuffered dimms in both non- parity x64 and ecc-optimized x72 configurations in the 168 pin form factor. cas latency = 2* -10 units f ck clock frequency 66 mhz t ck2 clock cycle 15 ns t ac2 clock access time 11.3 ns * sdram cas latency = 2; dimm cas latency = 3 . discontinued (4/1/00 - last order; 7/31/00 - last ship)
ibm13q32734bca 32m x 72 registered sdram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 2 of 15 04k8918.c75665b 6/99 card outline 1 101 16 116 17 117 (front) (back) 78 178 79 179 100 200 discontinued (4/1/00 - last order; 7/31/00 - last ship)
ibm13q32734bca 32m x 72 registered sdram module 04k8918.c75665b 6/99 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 3 of 15 pin description ck0 clock input (buffered through pll) dqm data mask (registered) cke0 clock enables (registered) v dd power (3.3v) ras row address strobe (registered) v ss ground cas column address strobe (registered) nc no connect we write enable (registered) pd1 - pd8 presence detect (buffered) s0, s1 chip selects (registered) pde presence detect enable a0 - a9, a11 address inputs (registered) id1 - id3 id bits a10/ap address input/auto precharge (reg) a12/bs1, a13/bs0 sdram bank selects (registered) dq0 - dq71 data input/output in, out physical detect (direct short) pinout x72 dimm pin# front side pin# back side pin# front side pin# back side pin# front side pin# back side pin# front side pin# back side 1 v dd 101 nc 26 v dd 126 dq53 51 v ss 151 ck0 76 dq16 176 v dd 2 nc 102 nc 27 dq51 127 dq52 52 ras 152 v dd 77 v ss 177 nc 3 nc 103 v ss 28 dq50 128 v dd 53 v ss 153 s1 78 nc 178 v ss 4 in 104 nc 29 v ss 129 dq47 54 nc 154 s0 79 nc 179 v ss 5 out 105 nc 30 dq49 130 dq46 55 a13/bs0 155 v ss 80 v dd 180 nc 6 id1 106 nc 31 dq48 131 v ss 56 v dd 156 a12/bs1 81 dq15 181 nc 7 id2 107 id3 32 v dd 132 dq45 57 a0 157 a10/ap 82 dq14 182 v dd 8 v ss 108 dq71 33 dq43 133 dq44 58 a1 158 v dd 83 v ss 183 dq11 9 dq67 109 dq70 34 dq42 134 v dd 59 v ss 159 a2 84 dq13 184 dq10 10 dq66 110 v ss 35 v ss 135 dq39 60 dq35 160 a3 85 dq12 185 v ss 11 v dd 111 dq69 36 dq41 136 dq38 61 dq34 161 v ss 86 v dd 186 dq9 12 dq65 112 dq68 37 dq40 137 v ss 62 v dd 162 dq31 87 dq7 187 dq8 13 dq64 113 v dd 38 v dd 138 dq37 63 dq33 163 dq30 88 dq6 188 v dd 14 v ss 114 nc 39 a4 139 dq36 64 dq32 164 v dd 89 v ss 189 dq3 15 dq63 115 v ss 40 a5 140 v dd 65 v ss 165 dq29 90 dq5 190 dq2 16 dq62 116 nc 41 v ss 141 a6 66 dq27 166 dq28 91 dq4 191 v ss 17 nc 117 dq59 42 a8 142 a7 67 dq26 167 v ss 92 v dd 192 dq1 18 dq61 118 dq58 43 a9 143 v ss 68 v dd 168 dq23 93 pde 193 dq0 19 dq60 119 v ss 44 v dd 144 a11 69 dq25 169 dq22 94 pd1 194 pd5 20 v dd 120 dq57 45 cke1 145 nc 70 dq24 170 v dd 95 pd2 195 pd6 21 nc 121 dq56 46 cke0 146 v dd 71 v ss 171 dq21 96 pd3 196 pd7 22 nc 122 v dd 47 v ss 147 dqm 72 dq19 172 dq20 97 pd4 197 pd8 23 v ss 123 dq55 48 cas 148 we 73 dq18 173 v ss 98 scl 198 v dd 24 nc 124 dq54 49 nc 149 v ss 74 v dd 174 nc 99 nc 199 nc 25 nc 125 v ss 50 v dd 150 nc 75 dq17 175 nc 100 v ss 200 nc ordering information part number organization clock cycle leads dimension power IBM13Q32734BCA-10Y 32mx72 66mhz gold 6.05" x 1.50" x 0.320" 3.3v discontinued (4/1/00 - last order; 7/31/00 - last ship)
ibm13q32734bca 32m x 72 registered sdram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 4 of 15 04k8918.c75665b 6/99 input/output functional description symbol type signal polarity function ck0 input pulse positive edge the system clock input. all of the sdram inputs are sampled on the rising edge of the clock. cke0 input level active high activates the ck0 signal when high and deactivates the ck0 signal when low. by deactivating the clock, cke0 low initiates the power down mode, suspend mode, or the self refresh mode. s0, s1 input pulse active low s0, s1 enables the command decoder when low and disables the command decoder when high. when the command decoder is disabled, new commands are ignored but previous oper- ations continue. ras, cas we input pulse active low when sampled at the positive rising edge of the clock, cas, ras, and we define the opera- tion to be executed by the sdram. a12/bs1 a13/bs0 input level select which sdram bank is to be active (bank 0 - bank3) a0 - a9, a11 a10/ap a12/bs1 a13/bs0 input level during a bank activate command cycle, a0-a10/ap and a11 defines the row address (ra0- ra11) when sampled at the rising clock edge. during a read or write command cycle, a0-a8 defines the column address (ca0-ca8) when sampled at the rising clock edge. in addition to the column address, a10/ap is used to invoke autoprecharge operation at the end of the burst read or write cycle. if a10/ap is high, auto- precharge is selected and bs0,bs1 defines the bank to be precharged. if a10/ap is low, auto- precharge is disabled. during a precharge command cycle, a10/ap is used in conjunction with bs0,bs1 to control which bank(s) to precharge. if a10/ap is high, all banks will be precharged regardless of the state of bs. if a10/ap is low, then bs0,bs1 is used to define which bank to precharge. dq0 - dq71 input output level data input/output pins operate in the same manner as on conventional dram dimms. dqm input pulse mask active high the data input/output mask places the dq buffers in a high impedance state when sampled high. in read mode, dqm has a latency of three clock cycles and controls the output buffers like an output enable. in write mode, dqm has a latency of one and operates as a word mask by allowing input data to be written if it is low but blocks the write operation if dqm is high. v dd , v ss supply power and ground for the module. presence detect pin value notes pd1 0 1 pd2 0 1 pd3 1 1 pd4 0 1 pd5 1 1 pd6 0 1 pd7 1 1 pd8 1 1 id1 1 2 id2 0 2 id3 0 2 1. 0 = driven to v ol , 1 = open 2. 0 = ground, 1 = open discontinued (4/1/00 - last order; 7/31/00 - last ship)
ibm13q32734bca 32m x 72 registered sdram module 04k8918.c75665b 6/99 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 5 of 15 block diagram: buffered 32mx72 ecc sdram dimm dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 dq28 dq29 dq30 dq31 i/o 0 i/o 1 i/o 2 i/o 3 d0 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 d1 d2 d3 d5 d6 d8 dq24 dq25 dq26 dq27 i/o 0 i/o 1 i/o 2 i/o 3 d7 dq36 dq37 dq38 dq39 dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 dq60 dq61 dq62 dq63 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 d10 d11 d13 d14 d16 dq56 dq57 dq58 dq59 i/o 0 i/o 1 i/o 2 i/o 3 d15 i/o 0 i/o 1 i/o 2 i/o 3 d4 i/o 0 i/o 1 i/o 2 i/o 3 d12 dq32 dq33 dq34 dq35 i/o 0 i/o 1 i/o 2 i/o 3 d9 dq68 dq69 dq70 dq71 i/o 0 i/o 1 i/o 2 i/o 3 d17 dq64 dq65 dq66 dq67 cke0 dqm ras cas we s0 register a0 - a10/ap feedback pll clock buffer ck0 a11 s1 pde v ss pd1 - pd8 3.3v a12/bs1 a13/bs0 notes: 1. a 10 ohm resistor is wired in series with all dqn lines near the card edge connector. 2. all clock lines from the pll clock buffer to the sdram devices are of equal length. 3. s0 tied to cs on drams d0-d17 (lower sdrams in stack). 4. s1 tied to cs on drams d0-d17 (upper sdrams in stack). 5. cke0 tied to cke on drams d0-d17 discontinued (4/1/00 - last order; 7/31/00 - last ship)
ibm13q32734bca 32m x 72 registered sdram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 6 of 15 04k8918.c75665b 6/99 absolute maximum ratings symbol parameter rating units notes v dd power supply voltage -0.3 to +4.6 v 1 v in input voltage -0.3 to +4.6 v 1 v out output voltage -0.3 to +4.6 v 1 t opr operating temperature 0 to +70 c 1 t stg storage temperature -55 to +125 c 1 p d power dissipation 16 w 1,2 i out short circuit output current 50 ma 1 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operati onal sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect r eli- ability. 2. maximum power is calcuated assuming both physical banks on the dimm are in auto refresh mode. recommended dc operating conditions (t a = 0 to 70 c) symbol parameter rating units notes min. typ. max. v dd supply voltage 3.3 3.6 v 1 v ih input high voltage 2.0 v dd + 0.3 v 1 v il input low voltage -0.3 0.8 v 1 1. all voltages referenced to v ss and vssq. capacitance (t a = 25 c, f=1mhz, v dd = 3.3v to 3.6v) symbol parameter max. units c i1 input capacitance (a0 - a9, a10/ap, a11) 15 pf c i2 input capacitance ( ras, cas, we, dqm, pde) 25 pf c i3 input capacitance ( s0, s1, cke0) 40 pf c i4 input capacitance (ck0) 10 pf c i01 input/output capacitance (dq0 - dq71) 25 pf c 01 output capacitance (pd1- pd8) 12 pf discontinued (4/1/00 - last order; 7/31/00 - last ship)
ibm13q32734bca 32m x 72 registered sdram module 04k8918.c75665b 6/99 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 7 of 15 output characteristics (t a = 0 to +70 c, v dd = 3.3v to 3.6v) symbol parameter min. max. units i i(l) input leakage current, any input (0.0v v in 3.6v), all other pins not under test = 0v -20 +20 m a i o(l) output leakage current (dq) (d out is disabled, 0.0v v out 3.6v) -2 +2 m a v oh output level (ttl) output h level voltage (i out = -2.0ma) 2.4 v dd v v ol output level (ttl) output l level voltage (i out = +2.0ma) 0.0 0.4 v i o(l) output leakage current (pd1 - pd8) -10 +10 m a operating, standby, and refresh currents (t a = 0 to +70 c, v dd = 3.3v to 3.6v) parameter symbol test condition value units notes operating current i cc1 1 bank operation t rc = t rc (min), t ck = min active-precharge command cycling without burst operation 2026 ma 1, 3, 4 precharge standby current in power down mode i cc2p cke v il (max), t ck = min, cs =v ih (min) 532 ma 2 i cc2ps cke v il (max), t ck = infinity, cs =v ih (min) 61 ma 2 precharge standby current in non-power down mode i cc2n cke 3 v ih (min), t ck = min, cs =v ih (min) 1396 ma 2, 5 i cc2ns cke 3 v ih (min), t ck = infinity, 241 ma 2, 6 no operating current (active state: 4 bank) i cc3n cke 3 v ih (min), t ck = min, cs =v ih (min) 1576 ma 2, 5 i cc3p cke v il (max), t ck = min, 604 ma 2, 7 operating current (burst mode) i cc4 t ck = min, read/ write command cycling, multiple banks active, gapless data,bl=4 2656 ma 1, 4, 8 auto (cbr) refresh current i cc5 t ck = min, t rc = t rc (min) cbr command cycling 4456 ma 2 self refresh current i cc6 cke 0.2v 61 ma 2, 8 1. the speci?ed values are for one dimm bank in the speci?ed mode, and the other dimm bank in active standby (i cc3n ). 2. the speci?ed values are for both dimm banks operating in the speci?ed mode. 3. these parameters depend on the cycle rate and are measured with the cycle determined by the minimum value of t ck and t rc . input signals are changed up to three times during t rc (min). 4. the specified values are obtained with the output open. 5. input signals are changed once during three clock cycles. 6. input signals are stable. 7. active standby current will be higher if clock suspend is entered during a burst read cycle (add 1ma per dq). 8. input signals are changed once during t ck(min) . discontinued (4/1/00 - last order; 7/31/00 - last ship)
ibm13q32734bca 32m x 72 registered sdram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 8 of 15 04k8918.c75665b 6/99 ac characteristics (t a = 0 to +70 c, v dd = 3.3v to 3.6v) 1. an initial pause of 200 m s is required after power-up, then a precharge all banks command must be given followed by a minimum of eight auto (cbr) refresh cycles before or after the mode register set opera- tion can begin. 2. ac timing tests have v il = 0.8v and v ih = 2.0v with the timing referenced to the 1.40v crossover point. 3. the transition time is measured between v ih and v il (or between v il and v ih ). 4. ac measurements assume t t =1ns. 5. in addition to meeting the transition rate speci?cation, the clock and cke0 must transit between v ih and v il (or between v il and v ih ) in a monotonic manner. ac characteristics diagram output input clock t oh t setup t hold t ac t lz 1.4v 0.8v 1.4v 1.4v 2.0v t t t cl t ch discontinued (4/1/00 - last order; 7/31/00 - last ship)
ibm13q32734bca 32m x 72 registered sdram module 04k8918.c75665b 6/99 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 9 of 15 clock and clock enable parameters symbol parameter value units notes min. max. t ck2 clock cycle time 15 66mhz ns t ac2 clock access time 11.3 ns 1, 2 t ch clock high pulse width 6.0 ns t cl clock low pulse width 6.0 ns t cks clock enable setup time 2.3 ns t ckh clock enable hold time 1.3 ns t cksp cke0 setup time (power down mode) 2.3 ns t t transition time (rise and fall) 1.4 10 ns t stab pll stabilization time 1 ms 1. cas latency defined at sdrams; dimm actually has cas latency of 3. 2. 50pf load. common parameters symbol parameter value units min. max. t s0 command setup time 2.3 ns t ch command hold time 1.3 ns t as address and bank select setup time 2.3 ns t ah address and bank select hold time 1.3 ns t rcd ras to cas delay 30 ns t rc bank cycle time 90 ns t ras active command period 60 100000 ns t rp precharge time 30 ns t rrd bank to bank delay time 20 ns t ccd cas to cas delay time 1 clk discontinued (4/1/00 - last order; 7/31/00 - last ship)
ibm13q32734bca 32m x 72 registered sdram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 10 of 15 04k8918.c75665b 6/99 mode register set cycle symbol parameter value units notes min. max. t rsc mode register set cycle time 20 ns 1 1. these parameters account for the number of clock cycles and depend on the operating frequency of the clock, as follows: the number of clock cycles = specified value of timing / clock period (count fractions as a whole number). read cycle symbol parameter value units notes min. max. t oh data out hold time 3.3 ns t lz data out to low impedance time 0.3 ns t hz2 data out to high impedance time 3.3 10.8 ns 1 t dqz dqm data out disable latency 3 clk 1. referenced to the time at which the output achieves the open circuit condition, not to output voltage levels. refresh cycle symbol parameter value units notes min. max. t ref refresh period 64 ms 1 t srex self refresh exit time 10 ns 1. 4096 cycles. write cycle symbol parameter value units min. max. t ds data in setup time 3.3 ns t dh data in hold time 2.3 ns t dpl2 data input to precharge 1 clk t dqw dqm write mask latency 1 clk discontinued (4/1/00 - last order; 7/31/00 - last ship)
ibm13q32734bca 32m x 72 registered sdram module 04k8918.c75665b 6/99 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 11 of 15 functional description and timing diagram refer to ibm 200-pin sdram registered dimm functional description and timing diagram (document 04k8917.c75644c, for sdram operation). clock frequency and latency symbol parameter value units notes f ck clock frequency 66.667 mhz t ck clock cycle time 15 ns t aa cas latency 3 t ck 1 t rcd ras to cas delay 2 t ck t rc bank cycle time 6 t ck t ras minimum bank active time 4 t ck t rp precharge time 2 t ck t dpl data in to precharge 1 t ck t dal data in to active/refresh 3 t ck t rrd bank to bank delay time 2 t ck t ccd cas to cas delay time 1 t ck t wl write latency 1 t ck t dqw dqm write mask latency 1 t ck t dqz dqm data disable latency 3 t ck t csl clock suspend latency 1 t ck 1. sdrams have t aa =2, but on-board dimm register adds one clock cycle presence detect read cycle symbol parameter value unit notes min max t pd pde to valid presence detect data 10 ns 1 t pdoff pde inactive to presence detects inactive 0 10 ns 2 1. measured with the specified current load and 100pf. 2. t pdoff (max) de?nes the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. discontinued (4/1/00 - last order; 7/31/00 - last ship)
ibm13q32734bca 32m x 72 registered sdram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 12 of 15 04k8918.c75665b 6/99 presence detect read cycle pde v ih v il pd1-pd8 v oh v ol valid presence detect t pdoff * * pd pins must be pulled high at next level of assembly t pd discontinued (4/1/00 - last order; 7/31/00 - last ship)
ibm13q32734bca 32m x 72 registered sdram module 04k8918.c75665b 6/99 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 13 of 15 layout drawing (200 pin dimm) r 1.00 .0393 note: all dimensions are typical unless otherwise stated. 2.0 .078 3.0 .118 detail a scale: 4/1 millimeters inches 6.35 .250 1.27 pitch .050 1.00 width .039 see detail a 1.5 38.1 (2) 0 3.1877 .1255 (2x) 4.00 .157 .3937 10.0 front 153.67 6.05 150.67 5.93 8.13 .320 max. side 1.27 0.10 .050 .004 + _ + _ 5.029 .198 min. discontinued (4/1/00 - last order; 7/31/00 - last ship)
ibm13q32734bca 32m x 72 registered sdram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 14 of 15 04k8918.c75665b 6/99 revision log revision contents of modi?cation 6/99 initial release. 6/18/99 updated notch dimensions line in layout drawing. discontinued (4/1/00 - last order; 7/31/00 - last ship)
intern ational business machines corp.1999 copyright printed in the united states of america all rights reserved ibm and the ibm logo are registered trademarks of the ibm corporation. this document may contain preliminary information and is subject to change by ibm without notice. ibm assumes no responsibility or liability for any use of the information contained herein. nothing in this document shall operate as an express or implied lice nse or indemnity under the intellectual property rights of ibm or third parties. the products described in this document are not inten ded for use in implantation or other direct life support applications where malfunction may result in direct physical harm or injury to persons. no warranties of any kind, including, but not limited to, the implied warranties of merchantability or fitness for a particular purpose, are offered in this document . for more information contact your ibm microelectronics sales representative or visit us on world wide web at http://www.chips.ibm.com ibm microelectronics manufacturing is iso 9000 compliant. a discontinued (4/1/00 - last order; 7/31/00 - last ship)

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